High-k/Ge p- & n-MISFETs with Strontium Germanide Interlayer for EOT Scalable CMIS Application

被引：22

作者：

Kamata, Yoshiki ^{[1
]}

Ikeda, Keiji ^{[1
]}

Kamimuta, Yuuichi ^{[1
]}

Tezuka, Tsutomu ^{[1
]}

机构：

[1] MIRAI Toshiba, Saiwai Ku, Kawasaki, Kanagawa 2128582, Japan

来源：

2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

D O I：

10.1109/VLSIT.2010.5556231

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-k/Ge with strontium germanide interlayer has been applied for both p- and n-MISFETs. The observed J(g)-EOT trend in the Ge-MISCAPs exhibits comparable or superior leakage characteristics to that of state-of-the-art HfSiON gate dielectrics on Si down to an EOT of 0.96nm. The drive current of the p-MISFETs increases with the EOT scaling around 1nm without mu(eff) degradation. Furthermore, reasonable V-th values are observed in both p-and n-MISFETs. These results suggest applicability of the SrGex interlayer to high-k/Ge CMISFETs.

引用

页码：211 / 212

页数：2

共 10 条

[1]

[Anonymous], 2009, 2009 IEEE INT ELECT

[2]

[Anonymous], 2009, IEDM

[3]

Huang J., 2008, 2008 Symposium on VLSI Technology, P82, DOI 10.1109/VLSIT.2008.4588571

[4]

KAMATA Y, 2009, MRS SPRING, pC2

[5]

KAMATA Y, 2009, VLSI S, P78

[6] High-k/Ge MOSFETs for future nanoelectronics [J].

Kamata, Yoshiki .

MATERIALS TODAY, 2008, 11 (1-2) :30-38

[7]

Kuzum D., 2009, IEDM, P453

[8]

Nakakita Y, 2008, INT EL DEVICES MEET, P877, DOI 10.1109/IEDM.2008.4796838

[9]

Suzuki M, 2005, INT EL DEVICES MEET, P445

[10]

Yasuda N., 2005, SOL STAT DEV MAT, P250

← 1 →