5.3-ps ECL and 71-GHz static frequency divider in self-aligned SEG SiGe HBT

被引：16

作者：

Ohue, E ^{[1
]}

Hayami, R ^{[1
]}

Oda, K ^{[1
]}

Shimamoto, H ^{[1
]}

Washio, K ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

PROCEEDINGS OF THE 2001 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 2001年

关键词：

D O I：

10.1109/BIPOL.2001.957850

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ECL gate with a delay time of 5.3 ps, the fastest yet reported for semiconductor technology, and based on a self-aligned SiGe HBT with an optimized SEG structure was developed. Maximum operating frequency of static frequency divider using this structure is up to 71 GHz.

引用

页码：26 / 29

页数：4

共 4 条

[1]

Crabbe E. F., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P83, DOI 10.1109/IEDM.1993.347393

[2] SIGE-HBTS WITH HIGH F(T) AT MODERATE CURRENT DENSITIES [J].

SCHUPPEN, A ;

GRUHLE, A ;

KIBBEL, H ;

ERBEN, U ;

KONIG, U .

ELECTRONICS LETTERS, 1994, 30 (14) :1187-1188

[3]

Washio K., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P557, DOI 10.1109/IEDM.1999.824215

[4]

WASHIO K, 2000, ISSCC, P210

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