0.12 μm P-MOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers

被引：15

作者：

Le Royer, C. ^{[1
]}

Clavelier, L. ^{[1
]}

Tabone, C. ^{[1
]}

Deguet, C. ^{[1
]}

Sanchez, L. ^{[1
]}

Hartmann, J. -M. ^{[1
]}

机构：

[1] CEA LETI Minatec, F-38054 Grenoble 9, France

来源：

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2007年

关键词：

D O I：

10.1109/ESSDERC.2007.4430977

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we report on deep sub-micron (gate length down to 0.12 mu m) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cut (TM) process to fabricate 200mm GeOI wafers with Ge thickness down to 60nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I-ON, I-OFF, Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.

引用

页码：458 / 461

页数：4

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