A 0.15 μm NAND flash technology with 0.11 μm2 cell size for 1 Gbit flash memory

被引：11

作者：

Choi, JD ^{[1
]}

Lee, JH ^{[1
]}

Lee, WH ^{[1
]}

Shin, KS ^{[1
]}

Yim, YS ^{[1
]}

Lee, JD ^{[1
]}

Shin, YC ^{[1
]}

Chang, SN ^{[1
]}

Park, KC ^{[1
]}

Park, JW ^{[1
]}

Hwang, CG ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Memory Business, Semicond R&D Ctr, Yongin City 449711, Kyungki Do, South Korea

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904430

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new 1Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 mum photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (similar to 80 nm) under the design rule and a high coupling ratio (similar to 0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layers interconnection leads to simple process and reduced steps. Thus, for the first time, a prototype 1Gb NAND flash memory with an extremely small cell size of 0.11 mum(2) has been achieved.

引用

页码：767 / 770

页数：4