A 7.7-ps CML using selective-epitaxial SiGe HBTs

被引：14

作者：

Ohue, E ^{[1
]}

Oda, K ^{[1
]}

Hayami, R ^{[1
]}

Washio, K ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

PROCEEDINGS OF THE 1998 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 1998年

关键词：

D O I：

10.1109/BIPOL.1998.741888

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The fastest CML-gate delay to date (7.7 ps) was achieved. This CML gate uses a fully-self-aligned SiGe-base HBT (with a92-GHz cutoff frequency and a 108-GHz maximum oscillation frequency) with a selectively-implanted collector through the base.

引用

页码：97 / 100

页数：4