Negative bias temperature instability (NBTI) in deep sub-micron p+-gate pMOSFETs

被引：25

作者：

Chen, YF ^{[1
]}

Lin, MH ^{[1
]}

Chou, CH ^{[1
]}

Chang, WC ^{[1
]}

Huang, SC ^{[1
]}

Chang, YJ ^{[1
]}

Fu, KY ^{[1
]}

Lee, MT ^{[1
]}

Liu, CH ^{[1
]}

Fan, SE ^{[1
]}

机构：

[1] United Microelect Corp, Hsinchu, Taiwan

来源：

2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT | 2000年

关键词：

negative bias temperature instability (NBTI); interface states; hole trapping; diffusion-reaction model;

D O I：

10.1109/IRWS.2000.911909

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The device degradation, characterized by threshold voltage shift (DeltaV(th)), in deep sub-micron p(+) polysilicon gate pMOSFETs due to negative bias temperature instability (NBTI) stress is studied. It is found that the negative threshold voltage shift tends to saturate with stress time. Both hydrogen ions and neutral atoms are believed to contribute to the generation of interface states. The I-V characteristics are compared before and after stresses and it shows that the interface degradation is symmetrical for S/D. In this work, a simple physical model is proposed to qualitatively explain the time evolution of the negative threshold voltage shift DeltaV(th). This saturation implies continued formation of oxide-trapped holes and the accumulation of positive fixed oxide charges, inhibiting further transport of hydrogen ions and resulting in a gradual decrease in interface trap formation. Moreover, the activation energy E-A and field-acceleration parameter are also extracted to establish a general phenomenological model to predict the device lifetime of pMOSFETs characterized by threshold voltage shift.

引用

页码：98 / 101

页数：4

共 12 条

[1] MECHANISM OF NEGATIVE-BIAS-TEMPERATURE INSTABILITY [J].