Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

被引：55

作者：

Kursun, V ^{[1
]}

Narendra, SG

De, VK

Friedman, EG

机构：

[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA

[2] Intel Corp, Microprocessor Res Labs, Hillsboro, OR 97124 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2003年 / 11卷 / 03期

关键词：

buck converter; dc-dc converter; dual supply voltage; high efficiency; integrated inductors; low power; low voltage; modeling of dc-dc converters; monolithic dc-dc conversion; multiple supply voltages; power supply; supply voltage scaling; switching dc-dc converters; voltage regulator;

D O I：

10.1109/TVLSI.2003.812289

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm(2) assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of,a high-efficiency buck converter on the same die with a dual-V-DD microprocessor is demonstrated to be feasible.

引用

页码：514 / 522

页数：9