Neuron-synapse IC chip-set for large-scale chaotic neural networks

被引:45
作者
Horio, Y [1 ]
Aihara, K
Yamamoto, O
机构
[1] Tokyo Denki Univ, Dept Elect Engn, Tokyo 1018457, Japan
[2] Grad Sch Frontier Sci, Dept Complex Sci & Engn, Tokyo 1138656, Japan
来源
IEEE TRANSACTIONS ON NEURAL NETWORKS | 2003年 / 14卷 / 05期
基金
日本科学技术振兴机构;
关键词
chaotic neural networks; mixed analog/digital system; chaos; large-scale neural networks;
D O I
10.1109/TNN.2003.816349
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10 000 neurons and 10 000(2) synaptic connections.
引用
收藏
页码:1393 / 1404
页数:12
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