Physics-based single-piece charge model for strained-Si MOSFETs

被引：11

作者：

Chandrasekaran, K ^{[1
]}

Zhou, X ^{[1
]}

Chiah, SB ^{[1
]}

Shangguan, W ^{[1
]}

See, GH ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2005年 / 52卷 / 07期

关键词：

bulk charge; charge balance; compact model; Debye length; flat-band; MOSFET; potential balance; SiGe; strained-silicon (s-Si); surface potential;

D O I：

10.1109/TED.2005.850611

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation to strong-inversion regions is presented. The model is formulated from regional solutions of the well-known Pao-Sah equation and unified with interpolation functions while keeping the physics in the derived flat-band voltages that depend on the device material and structural parameters, such as band gaps, conduction and valence band offsets, Ge mole fraction, layer thickness, and doping. The model is validated by comparison with numerical devices for a wide range of Ge mole fractions and s-Si layer thicknesses. It is shown that the model accurately describes the physical behavior of the surface potentials, terminal charges and capacitances, especially charge accumulation/depletion at the s-Si/SiGe interface that gives rise to the observed "plateau" in the capacitance-voltage characteristics.

引用

页码：1555 / 1562

页数：8

共 17 条

[1]

Chandrasekaran K, 2004, NSTI NANOTECH 2004, VOL 2, TECHNICAL PROCEEDINGS, P179

[2] C-V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design [J].

Chattopadhyay, S ;

Kwa, KSK ;

Olsen, SH ;

Driscoll, LS ;

O'Neill, AG .

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2003, 18 (08) :738-744

[3]

He J., 2003, P NSTI NAN SAN FRANC, V2, P302

[4]

Hoyt JL, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P23, DOI 10.1109/IEDM.2002.1175770

[5] Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si1-xGex virtual substrate [J].

Kawasaki, H ;

Ohuchi, K ;

Oishi, A ;

Fujii, O ;

Tsujii, H ;

Ishida, T ;

Kasai, K ;

Okayama, Y ;

Kojima, K ;

Adachi, K ;

Aoki, N ;

Kanemura, T ;

Hagishima, D ;

Fujiwara, M ;

Inaba, S ;

Ishimaru, K ;

Nagashima, N ;

Ishiuchi, H .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :169-172

[6] Strained-Si heterostructure field effect transistors [J].

Maiti, CK ;

Bera, LK ;

Chattopadhyay, S .

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1998, 13 (11) :1225-1246

[7] EFFECTS OF DIFFUSION CURRENT ON CHARACTERISTICS OF METAL-OXIDE (INSULATOR)-SEMICONDUCTOR TRANSISTORS [J].

PAO, HC ;

SAH, CT .

SOLID-STATE ELECTRONICS, 1966, 9 (10) :927-+

[8] BAND ALIGNMENTS OF COHERENTLY STRAINED GEXSI1-X/SI HETEROSTRUCTURES ON LESS-THAN-001-GREATER-THAN GEYSI1-Y SUBSTRATES [J].

PEOPLE, R ;

BEAN, JC .

APPLIED PHYSICS LETTERS, 1986, 48 (08) :538-540

[9] ELECTRONIC-BAND PARAMETERS IN STRAINED SI(1-X)GE(X) ALLOYS ON SI(1-Y)GE(Y) SUBSTRATES [J].

RIEGER, MM ;

VOGL, P .

PHYSICAL REVIEW B, 1993, 48 (19) :14276-14287

[10]

Rim K, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P43, DOI 10.1109/IEDM.2002.1175775

← 1 2 →