Parameterized high throughput function evaluation for FPGAs

This paper presents parameterized module- generators for pipelined function evaluation using lookup tables, adders, shifters, multipliers, and dividers. We discuss trade- offs involved between ( 1) full- lookup tables, ( 2) bipartite ( lookup- add) units, ( 3) lookup- multiply units, ( 4) shift- and- add based CORDIC units, and ( 5) rational approximation. Our treatment mainly focuses on explaining method ( 3), and briefly covers the background of the other methods. For lookup- multiply units, we provide equations for estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. A selection of the compared methods are implemented as part of the current PAM- Blox module generation environment. An example shows that the lookup- multiply unit produces competitive designs with data widths up to 20 bits when compared with shift- and- add based CORDIC units. Additionally, the lookup- multiply method or rational approximation can produce efficient designs for larger data widths when evaluating functions not supported by CORDIC.