Proposal of a single-transistor-cell-type ferroelectric memory using an SOI structure and experimental study on the interference problem in the write operation

A single-transistor-cell-type ferroelectric random access memory (FRAM) which consists of an array of metal-ferroelectric-semiconductor field effect transistors (MFSFETs) is proposed. In order to minimize the interference problem in the ''write/read'' operation, use of a silicon-on-insulator (SOI) structure is proposed, as well as optimizing the write and read methods partly using experimental results for ferroelectric capacitors. A key method for avoiding the interference problem is to generate a compensation pulse with a 1/3 amplitude and opposite polarity in the next timing to each write pulse. It is concluded from these considerations that the proposed structure is promising for use as a single-transistor-cell-type FRAM, if the electrical properties of a ferroelectric film on a Si substrate is as good as that on a Pt electrode.