A highly dense, high-performance 130nm node CMOS technology for large scale system-on-a-chip applications

被引：38

作者：

Ootsuka, F ^{[1
]}

Wakahara, S ^{[1
]}

Ichinose, K ^{[1
]}

Honzawa, A ^{[1
]}

Wada, S ^{[1
]}

Sato, H ^{[1
]}

Ando, T ^{[1
]}

Ohta, H ^{[1
]}

Watanabe, K ^{[1
]}

Onai, T ^{[1
]}

机构：

[1] Hitachi Ltd, Device Dev Ctr, Tokyo, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904385

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 130nm node CMOS technology with a self-aligned contact system is demonstrated. Tensile stress of the contact etch stop increases nFET's Ids, and reduces compressive stress caused by shallow trench isolation, which enhances pFET's Ids. A 1.92 mum(2) 6T-SRAM has been integrated with high performance transistors.

引用

页码：575 / 578

页数：4

共 5 条

[1]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[2] A modular 0.13 μm bulk CMOS technology for high performance and low power applications [J].

Han, LK ;

Biesemans, S ;

Heidenreich, J ;

Houlihan, K ;

Lin, C ;

McGahay, V ;

Schiml, T ;

Schmidt, A ;

Schroeder, UP ;

Stetter, M ;

Wann, C ;

Warner, D ;

Mahnkopf, R ;

Chen, B .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :12-13

[3]

Mehrotra M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P419, DOI 10.1109/IEDM.1999.824183

[4]

Onai T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P937, DOI 10.1109/IEDM.1999.824304

[5]

Scott G., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P827, DOI 10.1109/IEDM.1999.824277

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