A modular 0.13 μm bulk CMOS technology for high performance and low power applications

被引：37

作者：

Han, LK ^{[1
]}

Biesemans, S ^{[1
]}

Heidenreich, J ^{[1
]}

Houlihan, K ^{[1
]}

Lin, C ^{[1
]}

McGahay, V ^{[1
]}

Schiml, T ^{[1
]}

Schmidt, A ^{[1
]}

Schroeder, UP ^{[1
]}

Stetter, M ^{[1
]}

Wann, C ^{[1
]}

Warner, D ^{[1
]}

Mahnkopf, R ^{[1
]}

Chen, B ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Hopewell Junction, NY 12533 USA

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852749

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A leading-edge 0.13 mu m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 am lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 mu m(2) functional 6T-SRAM cell is demonstrated.

引用

页码：12 / 13

页数：2

共 4 条

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