Fabrication of size-tunable large-area periodic silicon nanopillar arrays with sub-10-nm resolution

被引:79
作者
Kuo, CW
Shiu, JY
Chen, PL
Somorjai, GA
机构
[1] Acad Sinica, Inst Appl Sci & Engn Res, Sect 2, Taipei 115, Taiwan
[2] Univ Calif Berkeley, Dept Chem, Berkeley, CA 94720 USA
[3] Lawrence Berkeley Natl Lab, Mat Sci & Chem Div, Berkeley, CA 94720 USA
关键词
D O I
10.1021/jp035468d
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
Here, we present a fabrication procedure that can produce large-area, size-tunable, periodic silicon nanopillar arrays, using metal templates that are created via nanosphere lithography. The size of the silicon nanopillars can be systematically controlled by an oxidation and etching process. The smallest size of nanopillars fabricated via this method is similar to9 nm, and the area covered with nanopillars is >1 cm(2). Using this approach and nanoimprint lithography, it is possible to pattern sub-10-nm metal nanoparticles with a particle density as high as 1 x 10(9) particles/cm(2).
引用
收藏
页码:9950 / 9953
页数:4
相关论文
共 38 条
[1]   Large-scale synthesis of a silicon photonic crystal with a complete three-dimensional bandgap near 1.5 micrometres [J].
Blanco, A ;
Chomski, E ;
Grabtchak, S ;
Ibisate, M ;
John, S ;
Leonard, SW ;
Lopez, C ;
Meseguer, F ;
Miguez, H ;
Mondia, JP ;
Ozin, GA ;
Toader, O ;
van Driel, HM .
NATURE, 2000, 405 (6785) :437-440
[2]   The formation of nano-dot and nano-ring structures in colloidal monolayer lithography [J].
Boneberg, J ;
Burmeister, F ;
Schafle, C ;
Leiderer, P ;
Reim, D ;
Fery, A ;
Herminghaus, S .
LANGMUIR, 1997, 13 (26) :7080-7084
[3]   Microporous materials - Electrochemically grown photonic crystals [J].
Braun, PV ;
Wiltzius, P .
NATURE, 1999, 402 (6762) :603-604
[4]  
Cheng JY, 2001, ADV MATER, V13, P1174, DOI 10.1002/1521-4095(200108)13:15<1174::AID-ADMA1174>3.0.CO
[5]  
2-Q
[6]   Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography [J].
Choi, YK ;
Zhu, J ;
Grunes, J ;
Bokor, J ;
Somorjai, GA .
JOURNAL OF PHYSICAL CHEMISTRY B, 2003, 107 (15) :3340-3343
[7]   A spacer patterning technology for nanoscale CMOS [J].
Choi, YK ;
King, TJ ;
Hu, CM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (03) :436-441
[8]   Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era [J].
Choi, YK ;
King, TJ ;
Hu, CM .
SOLID-STATE ELECTRONICS, 2002, 46 (10) :1595-1601
[9]   Nanoscale CMOS spacer FinFET for the terabit era [J].
Choi, YK ;
King, TJ ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (01) :25-27
[10]  
Connolly S, 1999, ADV MATER, V11, P1202, DOI 10.1002/(SICI)1521-4095(199910)11:14<1202::AID-ADMA1202>3.0.CO