1/f noise in CMOS transistors for analog applications

被引:111
作者
Nemirovsky, Y [1 ]
Brouk, I
Jakobson, CG
机构
[1] Technion Israel Inst Technol, Dept Elect Engn, IL-32000 Haifa, Israel
[2] Technion Israel Inst Technol, Dept Biomed Engn, IL-32000 Haifa, Israel
关键词
analog circuits; CMOS transistors; low noise; 1/f noise;
D O I
10.1109/16.918240
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two "low noise" CMOS processes of 2 mum and 0.5 mum technologies are compared and it is found that the more advanced process, with 0.5 mum technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.
引用
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页码:921 / 927
页数:7
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