Dynamic Task Mapping for MPSoCs

被引：95

作者：

de Souza Carvalho, Ewerson Luiz ^{[1
]}

Vilar Calazans, Ney Laert ^{[1
]}

Moraes, Fernando Gehm ^{[1
]}

机构：

[1] Pontificia Univ Catolica Rio Grande Sul FACIN PUC, Hardware Design Support Grp GAPH, Fac Informat, BR-90619900 Porto Alegre, RS, Brazil

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2010年 / 27卷 / 05期

关键词：

ENERGY-AWARE; NETWORK; CHIP;

D O I：

10.1109/MDT.2010.106

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.

引用

页码：26 / 35

页数：10

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