An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

被引：6

作者：

Kuriyama, H ^{[1
]}

Ashida, M ^{[1
]}

Tsutsumi, K ^{[1
]}

Maegawa, S ^{[1
]}

Maeda, S ^{[1
]}

Anami, K ^{[1
]}

Nishimura, T ^{[1
]}

Kohno, Y ^{[1
]}

Miyoshi, H ^{[1
]}

机构：

[1] Mitsubishi Elect Co, ULSI Lab, Itami, Hyogo 664, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1999年 / 46卷 / 05期

关键词：

asymmetric memory cell (AMC); cell ratio; complementary TFT (C-TFT); low-power; low-voltage; n-channel TFT; p-channel TFT; single-bit-line; SRAM; static noise margin (SNM);

D O I：

10.1109/16.760399

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a compact single-bit-line SRAM memory cell which we call an asymmetric memory cell (AMC) using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-μm design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT. © 1999 IEEE.

引用

页码：927 / 932

页数：6

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