Automatic synthesis of equipment recipes from specified wafer-state transitions

被引:2
作者
Davis, JC [1 ]
Mozumder, PK [1 ]
Burch, R [1 ]
Fernando, C [1 ]
Apte, PP [1 ]
Saxena, S [1 ]
Rao, S [1 ]
Vasanth, K [1 ]
机构
[1] Texas Instruments Inc, Ctr Adv Technol, Corp Res & Dev, Dallas, TX 75243 USA
关键词
D O I
10.1109/66.728548
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions, We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.
引用
收藏
页码:527 / 536
页数:10
相关论文
共 25 条
[11]  
KALIVAS J, 1995, ADAPTION SIMULATED A
[12]   CONJUGATE RESIDUAL METHOD FOR CONSTRAINED MINIMIZATION PROBLEMS [J].
LUENBERGER, DG .
SIAM JOURNAL ON NUMERICAL ANALYSIS, 1970, 7 (03) :390-+
[13]   AUTOMATED MALFUNCTION DIAGNOSIS OF SEMICONDUCTOR FABRICATION EQUIPMENT - A PLASMA ETCH APPLICATION [J].
MAY, GS ;
SPANOS, CJ .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1993, 6 (01) :28-40
[14]   A COMPARISON OF THREE METHODS FOR SELECTING VALUES OF INPUT VARIABLES IN THE ANALYSIS OF OUTPUT FROM A COMPUTER CODE [J].
MCKAY, MD ;
BECKMAN, RJ ;
CONOVER, WJ .
TECHNOMETRICS, 1979, 21 (02) :239-245
[15]   A MONITOR WAFER BASED CONTROLLER FOR SEMICONDUCTOR PROCESSES [J].
MOZUMDER, PK ;
SAXENA, S ;
COLLINS, DJ .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1994, 7 (03) :400-411
[16]   A SIMPLEX-METHOD FOR FUNCTION MINIMIZATION [J].
NELDER, JA ;
MEAD, R .
COMPUTER JOURNAL, 1965, 7 (04) :308-313
[17]  
POWELL MJD, 1977, DUNDEE C NUMERICAL A, P144
[18]  
QU M, 1996, 1 IEEE INT WORKSH ST
[19]   A branch-and-reduce approach to global optimization [J].
Ryoo, HS ;
Sahinidis, NV .
JOURNAL OF GLOBAL OPTIMIZATION, 1996, 8 (02) :107-138
[20]  
SAXENA S, 1997, P SPIE C IC MAN OCT