Processor-based built-in self-test for embedded DRAM

被引：54

作者：

Dreibelbis, J ^{[1
]}

Barth, J ^{[1
]}

Kalter, H ^{[1
]}

Kho, R ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Essex Jct, VT 05452 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 11期

关键词：

built-in self test (BIST); BIST architecture; BIST sequencer; DRAM macro; embedded DRAM; programmable BIST; redundancy allocation; test flow for embedded DRAM; two-dimensional redundancy;

D O I：

10.1109/4.726568

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A built-in self-test engine and test methodology have been del eloped for testing a family of high-bandwidth, high-density DRAM micros. The DRAM macros [1] range in size from 256 x 16 x 128 to 2 K x: 16 x 256 (Word x Bit x Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM highperformance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is architected for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations.

引用

页码：1731 / 1740

页数：10