Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield

被引：27

作者：

Croon, JA ^{[1
]}

Leunissen, LHA ^{[1
]}

Jurczak, M ^{[1
]}

Benndorf, M ^{[1
]}

Rooyackers, R ^{[1
]}

Ronse, K ^{[1
]}

Decoutere, S ^{[1
]}

Sansen, W ^{[1
]}

Maes, HE ^{[1
]}

机构：

[1] IMEC VZW, B-3001 Louvain, Belgium

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256855

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work experimentally investigates the impact of line-edge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.

引用

页码：227 / 230

页数：4

共 6 条

[1]

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[3]

HENSON K, 2002, P ESSDERC, P563

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[5]

Linton T, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P303, DOI 10.1109/IEDM.2002.1175839

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2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2000, :131-134

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