Non-volatile Si quantum memory with self-aligned doubly-stacked dots

被引：24

作者：

Ohba, R ^{[1
]}

Sugiyama, N ^{[1
]}

Uchida, K ^{[1
]}

Koga, J ^{[1
]}

Toriumi, A ^{[1
]}

机构：

[1] Toshiba Corp, Adv LSI Technol Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904319

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigate a novel Si quantum memory, in which floating gates are self-aligned doubly stacked Si dots. It is experimentally shown that the self-aligned double dot memory shows excellent charge retention. The retention improvement is explained by a theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot. It is also shown that charge retention is improved remarkably by lower dot size scaling without losing high-speed write/erase.

引用

页码：313 / 316

页数：4

共 6 条

[1]

Grabert H., 1992, Single Charge Tunneling

[2] Influence of channel depletion on the carrier charging characteristics in Si nanocrystal floating gate memory [J].

Ohba, R ;

Sugiyama, N ;

Koga, J ;

Uchida, K ;

Toriumi, A .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (3A) :989-993

[3]

OHBA R, 2000, SSDM, P122

[4]

OHBA R, 1999, SSDM, P86

[5]

Tiwari S, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P521, DOI 10.1109/IEDM.1995.499252

[6] Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits [J].

Uchida, K ;

Matsuzawa, K ;

Koga, J ;

Ohba, R ;

Takagi, S ;

Toriumi, A .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (4B) :2321-2324

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