Dynamic fault tolerance in FPGAs via partial reconfiguration

被引：46

作者：

Emmert, J ^{[1
]}

Stroud, C ^{[1
]}

Skaggs, B ^{[1
]}

Abramovici, M ^{[1
]}

机构：

[1] Univ Kentucky, Dept Elect Engn, Lexington, KY 40506 USA

来源：

2000 IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/FPGA.2000.903403

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in [1]. In STARs, the area under rest uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we rake this one step further: Once a fault tar multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies. *.

引用

页码：165 / 174

页数：10

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