Guidelines for the power constrained design of a CMOS tuned LNA

被引：9

作者：

Goo, JS ^{[1
]}

Oh, KH ^{[1
]}

Choi, CH ^{[1
]}

Yu, ZP ^{[1
]}

Lee, TH ^{[1
]}

Dutton, RW ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2000年

关键词：

D O I：

10.1109/SISPAD.2000.871260

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：269 / 272

页数：4

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