A C-switch cell for low-voltage and high-density SRAM's

被引：24

作者：

Kuriyama, H ^{[1
]}

Ishigaki, Y ^{[1
]}

Fujii, Y ^{[1
]}

Maegawa, S ^{[1
]}

Maeda, S ^{[1
]}

Miyamoto, S ^{[1
]}

Tsutsumi, K ^{[1
]}

Miyoshi, H ^{[1
]}

Yasuoka, A ^{[1
]}

机构：

[1] Mitsubishi Elect Corp, ULSI Lab, Itami, Hyogo 6648641, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1998年 / 45卷 / 12期

关键词：

D O I：

10.1109/16.735725

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-Switch) cell. The proposed SRAM cell features: 1) C-Switch in which an bn-channel bulk transistor and a p-channel TFT are combined in parallel; 2) single-bit-line architecture; 3) gate-all-around TFT (GAT) with large ON-current of mu A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-Switch cell is built with only a triple poly-Si and one metal process using 0.3 mu m design rules.

引用

页码：2483 / 2488

页数：6

共 14 条

[1] SUBTHRESHOLD SLOPE OF THIN-FILM SOI MOSFETS [J].

COLINGE, JP .

IEEE ELECTRON DEVICE LETTERS, 1986, 7 (04) :244-246

[2]

Ikeda S., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P809, DOI 10.1109/IEDM.1993.347276

[3]

ISHIMARU K, 1994, P S VLSI, P97

[4]

IZAWA T, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P941, DOI 10.1109/IEDM.1994.383256

[5] A C-Switch cell for low-voltage operation and high-density SRAMs [J].

Kuriyama, H ;

Ishigaki, Y ;

Fujii, Y ;

Maegawa, S ;

Maeda, S ;

Miyamoto, S ;

Tsutsumi, K ;

Miyoshi, H .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :279-282

[6]

KURIYAMA H, 1992, P S VLSI, P38

[7] A 0.4 MU-M GATE-ALL-AROUND TFT (GAT) USING A DUMMY NITRIDE PATTERN FOR HIGH-DENSITY MEMORIES [J].

MAEGAWA, S ;

IPPOSHI, T ;

MAEDA, S ;

NISHIMURA, H ;

TANINA, O ;

KURIYAMA, H ;

INOUE, Y ;

NISHIMURA, T ;

TSUBOUCHI, N .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1995, 34 (2B) :895-899

[8] Impact of mu A-ON-current gate-all-around TFT (GAT) for static RAM of 16Mb and beyond [J].

Maegawa, S ;

Ipposhi, T ;

Maeda, S ;

Kuriyama, H ;

Kohno, Y ;

Inoue, Y ;

Miyoshi, H ;

Hirao, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1996, 35 (2B) :910-914

[9] A 16-MB CMOS SRAM WITH A 2.3-MU-M(2) SINGLE-BIT-LINE MEMORY CELL [J].

SASAKI, K ;

UEDA, K ;

TAKASUGI, K ;

TOYOSHIMA, H ;

ISHIBASHI, K ;

YAMANAKA, T ;

HASHIMOTO, N ;

OHKI, N .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (11) :1125-1130

[10]

Subbanna S., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P441, DOI 10.1109/IEDM.1993.347315

← 1 2 →