What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

被引：94

作者：

Dambrine, G ^{[1
]}

Raynaud, C

Lederer, D

Dehan, M

Rozeaux, O

Vanmackelberg, M

Danneville, F

Lepilliet, S

Raskin, JP

机构：

[1] IEMN, F-59655 Villeneuve Dascq, France

[2] STMicroelect, F-38926 Crolles, France

[3] Catholic Univ Louvain, B-1348 Louvain, Belgium

[4] CEA, LETI, F-38054 Grenoble 9, France

来源：

IEEE ELECTRON DEVICE LETTERS | 2003年 / 24卷 / 03期

关键词：

RF CMOS; RF SOI; silicon device characterization;

D O I：

10.1109/LED.2003.809525

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length, reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

引用

页码：189 / 191

页数：3

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