A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a chip cores

被引：16

作者：

Takao, Y ^{[1
]}

Kudo, H ^{[1
]}

Mitani, J ^{[1
]}

Kotani, Y ^{[1
]}

Yamaguchi, S ^{[1
]}

Yoshie, K ^{[1
]}

Kawano, M ^{[1
]}

Nagano, T ^{[1
]}

Yamamura, I ^{[1
]}

Uematsu, M ^{[1
]}

Nagashima, N ^{[1
]}

Kadomura, S ^{[1
]}

机构：

[1] Fujitsu Ltd, Mfg Technol Dev Div, Tado, Mie 5110192, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904381

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 0.11 mu m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 <mu> m gate transistor, and 2.2 mu m(2) 6T-SRAM cell are realized by using KrF 248nm lithography, optical-proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63mA/ mu m and 0.28mA/ mu m are realized for nMOSFET and pMOSFET with 0.11 mu m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 mu m CMOS technology with copper/FSG interconnects.

引用

页码：559 / 562

页数：4

共 4 条

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Schroeder, UP ;

Stetter, M ;

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Warner, D ;

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2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :12-13

[2]

Imai K., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P667, DOI 10.1109/IEDM.1999.824240

[3]

KUDO H, 2000, P IITC, P271

[4]

Takao Y, 1997, 1997 SYMPOSIUM ON VLSI TECHNOLOGY, P11, DOI 10.1109/VLSIT.1997.623670

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