Electron Mobility in Surface- and Buried-Channel Flatband In0.53Ga0.47As MOSFETs With ALD Al2O3 Gate Dielectric

被引:36
作者
Bentley, Steven J. [1 ]
Holland, Martin [1 ]
Li, Xu [1 ]
Paterson, Gary W. [1 ]
Zhou, Haiping [1 ]
Ignatova, Olesya [1 ]
Macintyre, Douglas [1 ]
Thoms, Stephen [1 ]
Asenov, Asen [1 ]
Shin, Byungha [2 ]
Ahn, Jaesoo [2 ]
McIntyre, Paul C. [2 ]
Thayne, Iain G. [1 ]
机构
[1] Univ Glasgow, Nanoelect Res Ctr, Sch Engn, Glasgow G12 8QQ, Lanark, Scotland
[2] Stanford Univ, Dept Mat Sci & Engn, Stanford, CA 94305 USA
基金
英国工程与自然科学研究理事会;
关键词
Atomic layer deposition (ALD); electron mobility; InGaAs; MOSFET;
D O I
10.1109/LED.2011.2107876
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface- and buried-channel In0.53Ga0.47 As devices employing an atomic-layer-deposited Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm(2)/V . s and 6600 cm(2)/V . s at a carrier density of 3 x 10(12) cm(-2) were determined for the surface-and buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface-channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 x 10(12) cm(-2) before slowly dropping to around 2000 cm(2)/V . s at 1 x 10(13) cm(-2). We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.
引用
收藏
页码:494 / 496
页数:3
相关论文
共 12 条
[1]   Small-Signal Response of Inversion Layers in High-Mobility In0.53Ga0.47As MOSFETs Made With Thin High-κ Dielectrics [J].
Ali, Ashkar ;
Madan, Himanshu ;
Koveshnikov, Sergei ;
Oktyabrsky, Serge ;
Kambhampati, Rama ;
Heeg, Tassilo ;
Schlom, Darrell ;
Datta, Suman .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (04) :742-748
[2]   Enhancement-mode GaAs MOSFETs with an In0.3Ga0.7As channel, a mobility of over 5000 cm2/V•s, and transconductance of over 475 μS/μm [J].
Hill, Richard J. W. ;
Moran, David A. J. ;
Li, Xu ;
Zhou, Haiping ;
Macintyre, Douglas ;
Thoms, Stephen ;
Asenov, Asen ;
Zurcher, Peter ;
Rajagopalan, Karthik ;
Abrokwah, Jonathan ;
Droopad, Ravi ;
Passlack, Matthias ;
Thayne, Lain G. .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (12) :1080-1082
[3]  
Huang J., 2009, International Electron Device Meeting, P335
[4]   30-nm InAs PHEMTs With fT=644 GHz and fmax=681 GHz [J].
Kim, Dae-Hyun ;
del Alamo, Jesus A. .
IEEE ELECTRON DEVICE LETTERS, 2010, 31 (08) :806-808
[5]   Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals [J].
Kim, Eun Ji ;
Wang, Lingquan ;
Asbeck, Peter M. ;
Saraswat, Krishna C. ;
McIntyre, Paul C. .
APPLIED PHYSICS LETTERS, 2010, 96 (01)
[6]   Atomically abrupt and unpinned Al2O3/In0.53Ga0.47As interfaces: Experiment and simulation [J].
Kim, Eun Ji ;
Chagarov, Evgueni ;
Cagnon, Joel ;
Yuan, Yu ;
Kummel, Andrew C. ;
Asbeck, Peter M. ;
Stemmer, Susanne ;
Saraswat, Krishna C. ;
McIntyre, Paul C. .
JOURNAL OF APPLIED PHYSICS, 2009, 106 (12)
[7]   Exploring the ALD Al2O3/In0.53Ga0.47As and Al2O3/Ge interface properties: A common gate stack approach for advanced III-V/Ge CMOS [J].
Lin, D. ;
Waldron, N. ;
Brammertz, G. ;
Martens, K. ;
Wang, W. -E ;
Sioncke, S. ;
Delabie, A. ;
Bender, H. ;
Conard, T. ;
Tseng, W. H. ;
Lin, J. C. ;
Temst, K. ;
Vantomme, A. ;
Mitard, J. ;
Caymax, M. ;
Meuris, M. ;
Heyns, M. ;
Hoffmann, T. .
GRAPHENE, GE/III-V, AND EMERGING MATERIALS FOR POST-CMOS APPLICATIONS 2, 2010, 28 (05) :173-183
[8]  
Radosavljevic M., 2009, IEEE Conference Proceedings of International Electron Devices Meeting (IEDM), P1
[9]   Arsenic decapping and half cycle reactions during atomic layer deposition of Al2O3 on In0.53Ga0.47As(001) [J].
Shin, Byungha ;
Clemens, Jonathon B. ;
Kelly, Michael A. ;
Kummel, Andrew C. ;
McIntyre, Paul C. .
APPLIED PHYSICS LETTERS, 2010, 96 (25)
[10]   Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation [J].
Wong, HSP ;
Frank, DJ ;
Solomon, PM .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :407-410