Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

被引:62
作者
Pant, P [1 ]
Roy, RK
Chatterjee, A
机构
[1] Compaq Comp Corp, Shrewsbury, MA 01545 USA
[2] Mobilian Corp, Hillsboro, OR USA
[3] Georgia Inst Technol, Atlanta, GA 30332 USA
基金
美国国家科学基金会;
关键词
D O I
10.1109/92.924061
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.
引用
收藏
页码:390 / 394
页数:5
相关论文
共 12 条
[1]  
BURR JB, 1994, ISSCC DIG TECH PAP I, V37, P84, DOI 10.1109/ISSCC.1994.344717
[2]   MINIMIZING POWER-CONSUMPTION IN DIGITAL CMOS CIRCUITS [J].
CHANDRAKASAN, AP ;
BRODERSEN, RW .
PROCEEDINGS OF THE IEEE, 1995, 83 (04) :498-523
[3]  
CHEN Z, 1995, P S LOW POW EL, P78
[4]  
Cong J., 1994, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, V2, P408, DOI 10.1109/92.335010
[5]   Supply and threshold voltage scaling for low power CMOS [J].
Gonzalez, R ;
Gordon, BM ;
Horowitz, MA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (08) :1210-1216
[6]  
HENDENSTIERNA N, 1987, IEEE T COMPUT AID D, V6, P270
[7]   OPTIMIZATION OF HIGH-SPEED CMOS LOGIC-CIRCUITS WITH ANALYTICAL MODELS FOR SIGNAL DELAY, CHIP AREA, AND DYNAMIC POWER DISSIPATION [J].
HOPPE, B ;
NEUENDORF, G ;
SCHMITTLANDSIEDEL, D ;
SPECKS, W .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (03) :236-247
[8]   TRADING SPEED FOR LOW-POWER BY CHOICE OF SUPPLY AND THRESHOLD VOLTAGES [J].
LIU, D ;
SVENSSON, C .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (01) :10-17
[9]   Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits [J].
Pant, P ;
De, VK ;
Chatterjee, A .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (04) :538-545
[10]   AN EXACT SOLUTION TO THE TRANSISTOR SIZING PROBLEM FOR CMOS CIRCUITS USING CONVEX-OPTIMIZATION [J].
SAPATNEKAR, SS ;
RAO, VB ;
VAIDYA, PM ;
KANG, SM .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (11) :1621-1634