A 80μW/frame 104x128 CMOS imager front end for JPEG Compression

被引：13

作者：

Bandyopadhyay, A ^{[1
]}

Lee, J ^{[1
]}

Robucci, R ^{[1
]}

Hasler, P ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1465836

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a programmable 80 mu W/frame (3.3V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc). Floating-gate technology is used for on-chip kernel storage and also for performing low-power current-mode matrix multiplications. We demonstrate this IC as a front-end for JPEG compression and compare the performance of this imager to fully digital approaches.

引用

页码：5318 / 5321

页数：4

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