A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras

被引:72
作者
Kawahito, S [1 ]
Yoshida, M [1 ]
Sasaki, M [1 ]
Umehara, K [1 ]
Miyazaki, D [1 ]
Tadokoro, Y [1 ]
Murata, K [1 ]
Doushou, S [1 ]
Matsuzawa, A [1 ]
机构
[1] MATSUSHITA ELECT IND CO LTD,SEMICOND RES CTR,MORIGUCHI,OSAKA 570,JAPAN
关键词
A/D conversion; analog LSI; CMOS image sensor; discrete cosine transform; low power design; mobile computing; video compression;
D O I
10.1109/4.643661
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC), The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed, The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras, The 8 x 8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes, An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable level quantization after the 2-D DCT can be performed by the ADC at the same time, A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-mu m CMOS technology, Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed, The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB.
引用
收藏
页码:2030 / 2041
页数:12
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