Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing

Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacitance-voltage and source-drain current versus gate voltage characteristics of devices implanted with a dose of 1x10(16) cm(-2) or lower exhibit clear hysteresis characteristics at low electric field. The observed fluence dependence of the device electrical properties is interpreted in terms of the implanted oxide structure. (C) 2000 American Institute of Physics. [S0003-6951(00)05447-4].