A scalable 5-15 Gbps, 14-75 mW low-power I/O (transceiver in 65 nm CMOS

被引：98

作者：

Balamurugan, Ganesh ^{[1
]}

Kennedy, Joseph ^{[1
]}

Banerjee, Gaurab ^{[1
]}

Jaussi, James E. ^{[1
]}

Mansuri, Mozhgan ^{[1
]}

O'Mahony, Frank ^{[1
]}

Casper, Bryan ^{[1
]}

Mooney, Randy ^{[1
]}

机构：

[1] Intel Corp, Microprocessor Technol Labs, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 04期

关键词：

electrical signaling; high-speed I/O; I/O power optimization; inductive termination; low-power equalization; low-power I/O; passive clock distribution; power-efficient links; scalable circuits;

D O I：

10.1109/JSSC.2008.917522

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.

引用

页码：1010 / 1019

页数：10

共 25 条

[1]

[Anonymous], 2007, ISSCC

[2] Modeling and mitigation of jitter in multi-Gbps source-synchronous I/O links [J].

Balamurugan, G ;

Shanbhag, N .

21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, :254-260

[3] A scalable 5-15Gbps, 14-75mW low power I/O transceiver in 65nm CMOS [J].

Balamurugan, Ganesh ;

Kennedy, Joseph ;

Banerjee, Gaurab ;

Jaussi, James E. ;

Mansuri, Mozhgan ;

O'Mahony, Frank ;

Casper, Bryan ;

Mooney, Randy .

2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2007, :270-271

[4]

CASPER B, 2006, IEEE INT SOL STAT CI, P263

[5]

Dally W, 2008, DIGITAL SYSTEMS ENG

[6]

DALLY WJ, 1996, P HOT INT S AUG, P29

[7]

Doi Y, 2005, IEEE CUST INTEGR CIR, P131

[8]

Dorsey J., 2007, IEEE INT SOL STAT CI, P102

[9]

GONDI S, 2005, IEEE INT SOL STAT C, V1, P328

[10] Power-centric design of high-speed I/Os [J].

Hatamkhani, Hamid ;

Lambrecht, Frank ;

Stojanovic, Vladimir ;

Yang, Chih-Kong Ken .

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, :867-+

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