Bitline leakage equalization for sub-100nm caches

被引：18

作者：

Alvandpour, A ^{[1
]}

Somasekhar, D ^{[1
]}

Krishnamurthy, R ^{[1
]}

De, V ^{[1
]}

Borkar, S ^{[1
]}

Svensson, C ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, Linkoping, Sweden

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257157

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a leakage-tolerant circuit technique for embedded sub-100nm SRAM's. The proposed 8-transistor memory cells inject identical leakage currents into the differential bitlines. During a read operation, the active leakage-equalization eliminates the differential offset voltage due to leakage currents. This results in a fast differential voltage development on the input of sense amplifiers and therefore a faster read operation. The proposed technique significantly relaxes the conventional constraint on device I-ON/I-OFF ratio versus number of memory-cells per bitline. Consequently, a large number of leaky memory cells can share a single bitline eliminating the need for aggressive bitline partitioning. Up to 80% faster differential voltage development has been observed for 100nm 256-cells bitlines.

引用

页码：401 / 404

页数：4

共 5 条

[1] A bitline leakage compensation scheme for low-voltage SRAMs [J].