A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications

被引:138
作者
Chien, G [1 ]
Gray, PR
机构
[1] Marvell Semicond, Sunnyvale, CA 94086 USA
[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
基金
美国国家科学基金会;
关键词
delay-locked loops; local oscillator; frequency synthesizer; frequency multiplier; phase noise; integrated wireless transceiver; CMOS RF;
D O I
10.1109/4.890315
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A monolithic CMOS local oscillator utilizing a delay-locked loop (DLL)-based frequency multiplier technique to synthesize a 900-MHz carrier frequency with a low close-in phase noise is described. The prototype, implemented in a double-poly five-metal 0.35-mum CMOS technology, achieves a -123 and -127 dBc/Hz phase noise at 60 and 330 kHz offset frequencies, respectively, while dissipating 130 mW from a 3.3-V supply. This prototype satisfies the specification of the IS-137 AMPS/TDMA dual-mode standard.
引用
收藏
页码:1996 / 1999
页数:4
相关论文
共 8 条
[1]  
ABIDI AA, 1997, DIG TECH PAPERS INT, P118
[2]  
Chien G., 2000, THESIS U CALIFORNIA
[3]   A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors [J].
Craninckx, J ;
Steyaert, MSJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (05) :736-744
[4]  
LIN L, 2000, DIG TECH PAPERS, P204
[5]  
ROFOUGARAN A, 1996, DIG TECH PAPERS INT, P392
[6]  
Rudell J. C., 1997, IEEE J SOLID-ST CIRC, V32, P2701
[7]   AN 8-BIT 100-MHZ FULL-NYQUIST ANALOG-TO-DIGITAL CONVERTER [J].
VANDEPLASSCHE, RJ ;
BALTUS, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (06) :1334-1344
[8]  
WEIGANDT TC, 1994, INT S CIRC SYST JUN, P118