High-performance high-κ/Metal gates for 45nm CMOS and beyond with gate-first processing

被引：85

作者：

Chudzik, M. ^{[1
]}

Doris, B. ^{[2
]}

Mo, R. ^{[1
]}

Sleight, J. ^{[2
]}

Cartier, E. ^{[2
]}

Dewan, C. ^{[2
]}

Park, D. ^{[2
]}

Bu, H. ^{[2
]}

Natzle, W. ^{[2
]}

Yan, W. ^{[1
]}

Ouyang, C. ^{[2
]}

Henson, K. ^{[1
]}

Boyd, D. ^{[1
]}

Callegari, S. ^{[2
]}

Carter, R. ^{[3
]}

Casarotto, D. ^{[1
]}

Gribelyuk, M. ^{[1
]}

Hargrove, M. ^{[3
]}

He, W. ^{[1
]}

Kim, Y. ^{[2
]}

Linder, B. ^{[2
]}

Moumen, N. ^{[1
]}

Paruchuri, V. K. ^{[2
]}

Stathis, J. ^{[2
]}

Steen, M. ^{[2
]}

Vayshenker, A. ^{[1
]}

Wang, X. ^{[2
]}

Zafar, S. ^{[2
]}

Ando, T. ^{[4
]}

Iijimas, R. ^{[5
]}

Takayanagi, M. ^{[5
]}

Narayanan, V. ^{[2
]}

Wise, R. ^{[1
]}

Zhang, Y. ^{[2
]}

Divakaruni, R. ^{[1
]}

Khare, M. ^{[2
]}

Chen, T. C. ^{[2
]}

机构：

[1] IBM Semicond Res & Dev Ctr SDRC, IBM Syst & Technol Div, Hopewell Jct, NY 12533 USA

[2] TJ Watson Res Ctr, Res Div, Yorktown Hts, NY 10598 USA

[3] Adv Micro Devices Inc, Hopewell Jct, NY 12533 USA

[4] Sony Elect Inc, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

[5] Toshiba Amer Elect Components Inc, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339689

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Gate-first integration of band-edge (BE) high-kappa/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-kappa/metal gates (HK/MG) enabled by the thinnest T-inv (< 12 angstrom) for BE nFET devices to-date, consistent with simulations showing the need for < 14 angstrom Tin, at Lgate < 35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-kappa/metal gate pFET's fabricated with gate-first high thermal budget processing with thin Tin, (< 13A) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-kappa/metal gate nFET's into CMOS devices yielded large SRAM arrays.

引用

页码：194 / +

页数：2

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