A 2.05 um2 full CMOS ultra-low power SRAM cell with 0.15um generation single gate CMOS technology

被引：4

作者：

Jang, JH ^{[1
]}

Kim, HS ^{[1
]}

Baek, HC ^{[1
]}

Na, JJ ^{[1
]}

Lee, KH ^{[1
]}

Seo, DS ^{[1
]}

Kim, KJ ^{[1
]}

Kim, KT ^{[1
]}

Shin, YS ^{[1
]}

Hwang, CG ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, SRAM1 Team, Yongin City 449711, Kyungki Do, South Korea

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904386

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a 2.05 um(2) full-CMOS ultra-low power SRAM Cell, which is probably the world-smallest, using 0.15um generation single gate CMOS technology. The technology includes i) 0.15um direct contact (to active region and gate poly) implemented by phase shift mask (PSM) and the shrinkage of contact by photo-resist (PR) reflow, ii) W-damascened local interconnection with 0.30um pitch, iii)careful optimization of 0.17um gate length buried channel (BC) pMOS to minimize the leakage current, while excludes self-aligned contact, Co-salicide, and rapid thermal annealing (RTA).

引用

页码：579 / 582

页数：4