High hole mobilities in fully-strained Si1-xGex layers (0.3 < x < 0.4) and their significance for SiGe pMOSFET performance

Materials studies, hole transport measurements, and process and device simulations have been employed to determine the optimum epitaxial architecture of a fully-pseudomorphic Si/SiGe pMOSFET heterostructure that is intended for application in a near-standard CMOS process, Numerical simulations have shown that SiGe inter-diffusion severely limits the Ge content that can be achieved in a practical process flow. The SiGe hole wave-functions have been calculated and it is shown that hole confinement effects become very significant for SiGe layers less than 5 nm thick. Furthermore, estimates of the barrier penetration by the hole wave-function indicate that the beneficial effects of the buried-channel structure upon the hole mobility would be significantly reduced for Si cap thickness less than 2 mn, Buried-channel SiGe pMOSFETs are known to suffer from parallel conduction in the Si capping layer and calculations of the charge distribution indicate that high Ge contents (> 30%) and thin Si cap thickness (<3 nm) are required in order to confine all of the inversion charge to the SiGe layer. The hole drift mobility has been measured at room temperature for fully-strained Si(1-x)Ge(x) layers with a range of alloy contents (0.3 < x < 0.4) and with hole densities between 3 x 10(11) cm(-2) and 4 x 10(12) cm(-2). The measured room temperature cm mobilities are consistently higher than the equivalent Si inversion Layer mobilities and these results have been incorporated into two-dimensional (2-D) device simulations in order to understand their significance for SiGe pMOS device performance. It is found that improvements in current drive can be obtained, but only for the most aggressive vertical architectures. For Si cap thickness greater than 1.5 nm, parallel conduction in the cap layer counteracts much of the advantage of the high mobility channel and, even for thin Si caps, velocity saturation effects at high lateral electric fields significantly limit the current drive of a SiGe pMOSFET to values close to that of the conventional Si device. The diminished gate control, due to the inclusion of the cap layer, and the smaller SiGe bandgap also lead to a significant deterioration of the subthreshold characteristics.