Validation of Turandot, a fast processor model for microarchitecture exploration

被引：20

作者：

Moudgill, M ^{[1
]}

Bose, P ^{[1
]}

Moreno, JH ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

1999 IEEE INTERNATIONAL PERFORMANCE, COMPUTING AND COMMUNICATIONS CONFERENCE | 1999年

关键词：

D O I：

10.1109/PCCC.1999.749471

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe the results in validating the performance projections from a parameterized tr ace-driven simulation model of a speculative out-of-order superscalar processor; which has been developed with the objective of acting as a microarchitecture exploration tool. Because of its objective, the model -called Turandot- has been designed to deliver much higher simulation speed than what is achieved from detailed (RTL) processor models. We summarize the validation methodology used, and present experimental data gathered in the calibration of one processor organization modeled with Turandot against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, Turandot is within 5% of the results reported by the reference model while exhibiting a speed-up factor of about 70.

引用

页码：451 / 457

页数：7