Digital sliding-mode observer implementation using FPGA

This paper details the digital implementation of a new observation strategy of the flying capacitor voltages dedicated to stacked multicell converters (SMC). This particular topology relies on the use of flying capacitors so as to equally share the voltage constraint on several semiconductors and increase the number of output levels. However, the SMC appropriate operation is guaranteed by the stability of the flying capacitor voltage levels, and the current flow creates variations of those quantities. The idea is therefore to develop an accurate estimation technique that avoids the utilization of differential sensors and allows the active control of the intermediate voltages. The observation has to meet several criteria. It must particularly reproduce in a quasi-analog way the dynamic of those quantities to enable the proper operation of the active control algorithm. The actual research scope thus focuses on the sliding mode observation of the flying capacitor voltages by means of phase current measurements. This paper summarizes the observer design, its digitizing, and the field-programmable gate array (FPGA) implementation. It also presents an interesting Very High Speed Integrated Circuit Hardware Description Language (VHDL)-Saber Cosimulation tool that allows validating the VHDL code before being downloaded in the FPGA of the physical system. The last section illustrates and emphasizes the performance and ruggedness of the implemented algorithm through promising experimental results.