Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

被引:62
作者
Mori, S
Araki, YY
Sato, M
Meguro, H
Tsunoda, H
Kamiya, E
Yoshikawa, K
Arai, N
Sakagami, E
机构
[1] Semiconduct. Device Eng. Laboratory, Toshiba Corporation
关键词
D O I
10.1109/16.477592
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top-oxide structure is preferable to minimize degradation due to defects, It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 mm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
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收藏
页码:47 / 53
页数:7
相关论文
共 11 条
[11]  
YOSHIKAWA K, 1991, VLSI S DIG TECH PAPE, P79