Comparisons of FIR and IIR implementations of a subtraction-based stimulus artifact rejection algorithm

Finite impulse response (FIR) and infinite impulse response (IIR) temporal filtering techniques are investigated to assess the feasibility of very-large-scale-integrated (VLSI) implementation of a subtraction-based stimulus artifact rejection (SAR) algorithm in implantable, closed-loop neuroprostheses. The two approaches are compared in terms of their system architectures, overall performances, and the associated computational costs. Pre-recorded neural data from an Aplysia californica are used to demonstrate the functionality of the proposed implementations. Digital building blocks for an FIR-based system are also simulated in a 0.18-mu m CMOS technology, showing a total power consumption of <5 mu W from a 1-V supply and a die area of similar to 1.5mm(2). An HR-based system can further reduce the required power consumption and die area.