LOGIC product yield analysis by wafer bin map pattern recognition supervised neural network

被引：13

作者：

Chen, FL ^{[1
]}

Lin, SC ^{[1
]}

Doong, KYY ^{[1
]}

Young, KL ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Hsinchu, Taiwan

来源：

2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ISSM.2003.1243336

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Wafer Bin Maps (WBMs) are important for yield improvement to trace root causes. The characteristic of WBMs patterns are formed by processes, so process engineers can collect clues from the patterns and correlate them with specific processes, and this can save much time and efforts in finding the root causes. However, the existing learning algorithms have the main shortage of product dependency. For this reason, this work adopted a supervised learning methodology to develop an on-line WBMs pattern recognition system that maps WBMs into 70x70 binary images to solve this issue. Furthermore, this work also proposed a learning scheme to recognize repeating failures that are usually viewed as random pattern in the existing approaches.

引用

页码：501 / 504

页数：4

共 10 条

[1] A neural-network approach to recognize defect spatial pattern in semiconductor fabrication [J].