Enhancement of PMOS device performance with poly-SiGe gate

被引：22

作者：

Lee, WC ^{[1
]}

Watson, B

King, TJ

Hu, CM

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[2] Morgan State Univ, Dept Elect Engn, Baltimore, MD 21251 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 1999年 / 20卷 / 05期

基金：

美国国家科学基金会;

关键词：

hole mobility; poly-SiGe;

D O I：

10.1109/55.761024

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Poly-Si and poly-Si0.75Ge0.25-gated PMOS transistors with a very thin gate oxide of 29 Angstrom were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I-d-V-d characteristics mere observed for the poly SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V-g. T-ox, V-th, and V-fb Both reduced GDE and superior hole mobility contribute to the enhanced performance.

引用

页码：232 / 234

页数：3

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