Suppressed threshold voltage roll-off characteristic of 40nm gate length ultrathin SOI MOSFET

被引：9

作者：

Ishii, K ^{[1
]}

Suzuki, E ^{[1
]}

Kanemaru, S ^{[1
]}

Maeda, T ^{[1
]}

Nagai, K ^{[1
]}

Sekigawa, T ^{[1
]}

机构：

[1] Electrotech Lab, Tsukuba, Ibaraki 3058586, Japan

来源：

ELECTRONICS LETTERS | 1998年 / 34卷 / 21期

关键词：

D O I：

10.1049/el:19981433

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The authors have experimentally demonstrated a highly suppressed threshold voltage roll-off characteristic of a 40nm gate length ultrathin (11nm) silicon-on-insulator n-MOSFET. It is observed that Delta V-th is only 0.2V when compared with a long gate length (150nm) device. The marked effectiveness of an ultrathin SOI channel is experimentally confirmed to suppress the short. channel effect.

引用

页码：2069 / 2070

页数：2

共 8 条

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