SCALING THE SI MOSFET - FROM BULK TO SOI TO BULK

被引:660
作者
YAN, RH [1 ]
OURMAZD, A [1 ]
LEE, KF [1 ]
机构
[1] AT&T BELL LABS, DEPT HIGH SPEED ELECTR RES, HOLMDEL, NJ 07733 USA
关键词
D O I
10.1109/16.141237
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Scaling the Si MOSFET is revisited. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to undesirable large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, we note the important concept of controlling horizontal leakage through vertical structures. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of Vertical Doping Engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping.
引用
收藏
页码:1704 / 1710
页数:7
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