MOCVD-grown wider-bandgap capping layers in Hg1-xCdxTe long-wavelength infrared photoconductors

The use of MOCVD-grown wider-bandgap Hg1-xCdxTe as a capping layer for long-wavelength infrared (LWIR) Hg1-xCdxTe photoconductors has been studied using both theoretical and experimental results. A device model is derived which shows that in the presence of a suitable energy barrier between the Hg1-xCdxTe infrared absorbing layer and the overlaying passivation layer, the high surface recombination rate which is usually present at the semiconductor/passivant interface is prevented from having a significant effect on device performance. The energy barrier, which repels photogenerated minority carriers from the semiconductor surface, is introduced by employing an n-type Hg1-xCdxTe wafer which consists of a wider-bandgap capping layer that is grown in situ by MOCVD on an LWIR absorbing layer. The derived model allows the responsivity to be calculated by taking into account surface recombination at both the front and back interfaces, thickness of capping and absorbing layers, recombination at the heterointerface, and variations in equilibrium electron concentration. Calculations show that for an x = 0.22 Hg(1-x)C(d)xTe absorbing layer, the optimum capping layer consists of x greater than or equal to 0.25 and a thickness of the order of 0.1 to 0.2 mu m. Experimental results are presented for x = 0.22 n-type Hg1-xCdxTe conventional single-layer LWIR photoconductors, and for heterostructure photoconductors consisting of an LWIR absorbing layer of x = 0.22 capped by an n-type layer of x = 0.31. The model is used to extract the recombination velocities at the heterointerface and the semiconductor/substrate interface, which are determined to be 250 cm s(-1) and 100 cm s(-1) respectively. The experimental data clearly indicate that the use of a heterostructure barrier between the overlaying passivation layer and the underlying LWIR absorbing layer produces detectors that exhibit much higher performance and are insensitive to the condition of the semiconductor/passivant interface.