A CMOS 3.5Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting

被引:8
作者
Choi, JS [1 ]
Hwang, MS [1 ]
Jeong, DK [1 ]
机构
[1] Seoul Natl Univ, Sch Elect Engn, Seoul 151742, South Korea
来源
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年
关键词
CMOS; adaptive cable equalizer; joint adaptation; varactor; common mode biasing;
D O I
10.1109/VLSIC.2003.1221174
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18um mixed-mode CMOS process. The realized active area is 0.48mm x 0.73mm. The filter cell operates up to 5Gbps and the adaptive equalizer operates up to 3.5Gbps over a 15-m RG-58 coaxial cable with a 1.8V supply and 80mW power dissipation.
引用
收藏
页码:103 / 106
页数:4
相关论文
共 10 条
[1]  
Akcasu O. E., 1993, U.S. Patent, Patent No. [5,208,725, 5208725]
[2]  
BABANEZHAD JN, IEEE 1998 CICC, P343
[3]   Transmitter equalization for 4-Gbps signaling [J].
Dally, WJ ;
Poulton, J .
IEEE MICRO, 1997, 17 (01) :48-56
[4]   A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver [J].
Farjad-Rad, R ;
Yang, CKK ;
Horowitz, MA ;
Lee, TH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (05) :757-764
[5]  
HARTMAN GP, IEEE 1999 ISCAS, P97
[6]   Integrated circuits for data transmission over twisted-pair channels [J].
Johns, DA ;
Essig, D .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (03) :398-406
[7]  
KUDOH Y, 2002 SOVC, P64
[8]  
SHAKIBA MH, 1999 IEEE ISSCC, P396
[9]  
SONNTAG J, IEEE 2002 CICC, P363
[10]   FULL-WAVE PRECISION RECTIFICATION THAT IS PERFORMED IN CURRENT DOMAIN AND VERY SUITABLE FOR CMOS IMPLEMENTATION [J].
WANG, ZH .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1992, 39 (06) :456-462