Extending gate dielectric scaling limit by NO oxynitride: Design and process issues for sub-100 nm technology

In this work, the characteristics of CMOSFETs with heavily nitrided NO oxynitrides, which meet performance and manufacturability criteria, are investigated. The gate leakage current in NO oxynitride with sufficient nitridation is reduced by a factor of more than 10 when compared with thermal oxide of equivalent thickness. It is projected that NO oxynitride can be scaled down to an effective physical oxide thickness of 1.5 nm while maintaining strong resistance to B penetration and low standby power. Significantly enhanced diffusion of B in the Si substrate is observed during NO annealing. It is revealed that the magnitude of the diffusivity enhancement strongly depends on the NO annealing temperature, suggesting that the NO anneal process should be carefully optimized to minimize the channel/well dopant redistribution. Additionally, optimum device design for CMOSFETs with heavily nitrided NO oxynitrides is studied. It is experimentally demonstrated that careful tailoring of doping profiles for halo and S/D regions is required to minimize short-channel device degradation in heavily nitrided devices.