On the application of symbolic techniques to the multiple fault location in low testability analog circuits

A new approach for the multiple fault location in linear analog circuits is proposed. It presents the characteristic of using classical numerical procedures together with symbolic analysis techniques, which result particularly useful in the parametric fault diagnosis field. The proposed approach is based on the k-fault hypothesis and is provided with efficient algorithms for fault location also in the case of low testability circuits. The developed algorithms have been used for realizing a software package prototype which implements a fully automated system for the fault location in linear analog circuits of moderate size.