Quantized conductance in a small one-dimensional Si wire on a thin silicon-on-insulator substrate fabricated using SiN-film-masked oxidation

A new fabrication technique for a one-dimensional (1D) Si wire on a separation-by-implanted-oxygen (SIMOX) substrate, which is effective in reducing the parasitic resistance caused by the thin lead Si regions, is proposed. Thermal oxidation of the Si layer on which a stacked structure of SiO2 and SIN films is formed does not reduce the thickness of the wide two-dimensional (2D) Si layer, though the 1D wire becomes thinner by the oxidation. A MOS-type 1D Si wire fabricated using this technique shows a clear step-like conductance as a function of gate voltage. Though the measured conductance step is slightly lower than the theoretically predicted value, it is much larger than previously reported values. The inherent conductance of the 1D wire can be extracted from the measured overall conductance owing to low parasitic resistance. The first conductance step thus obtained agrees well with the theoretical value of 4e(2)/h.